`timescale 1ns/1ps
module tb_beep();

    reg sys_clk = 1'b0;
    reg sys_rst_n;
    reg key;
    wire beep;

    beep#(.CNT_MAX(20'd1_000)) u_beep(
        .sys_clk(sys_clk),
        .sys_rst_n(sys_rst_n),
        .key(key),
        .beep(beep)
    );

    always #10 sys_clk = ~sys_clk;

    initial begin
        sys_rst_n <= 1'b0;
        key <= 1'b1;
        #1000
        sys_rst_n <= 1'b1;
        key <= 1'b0;
        #1000
        key <= 1'b1;
        #1000
        key <= 1'b0;
        #10000
        key <= 1'b1;
        #10000
        key <= 1'b0;
        #20000
        key <= 1'b1;
        #20000
        key <= 1'b0;
        #30000
        key <= 1'b1;
        #30000
        key <= 1'b0;
        #40000
        key <= 1'b1;
        #40000
        key <= 1'b0;
    end
endmodule